1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device composed of standard cells arranged therein and to a power source wiring method for the semiconductor integrated circuit device.
2. Description of the Prior Art
In recent years, as digital circuits have become higher in speed and functionality, semiconductor integrated circuit devices have also become increasingly higher in speed and integration degree. To increase the integration degree of a semiconductor integrated circuit device, a fabrication process therefor has been scaled down year after year and, consequently, the width of a signal line used in the semiconductor integrated circuit device has been increasingly reduced. In addition, the increased speed of the semiconductor integrated circuit device has increased an amount of a current flowing in the signal line. Thus, when the width of the signal line has been reduced and the amount of the current has increased, the density of a current in wiring in the semiconductor integrated circuit device has increased so that a break in wiring and a short circuit therein due to electromigration have caused problems.
On the other hand, with the increase in the speed of the semiconductor integrated circuit device, it has become important to reduce variations (clock skew) in the delay of a clock signal in the semiconductor integrated circuit. The clock skew is the difference between the arrival times of the clock signal at two flip-flops operating in synchronization. When the clock skew is large, it may cause a reduction in operating frequency and even the misoperation of a circuit.
As a technology for reducing the clock skew, there is used a technique termed a clock tree which forms a tree-like clock distribution path with a plurality of relay buffers and distributes the clock from a clock supply source to the flip-flops. The clock tree reduces the clock skew by constructing a semiconductor integrated circuit device such that wiring lengths from the clock supply source to the terminal flip-flops are equal (see, e.g., Japanese Laid-Open Patent Publication No. HEI 6-204435).
Even in such a clock tree with equal wiring lengths, when wiring capacitances are different under the influence of surrounding wiring lines or the gate capacitances of cells driven by the relay buffers are different, the clock skew undesirably occurs depending on a delay in the clock tree portion. Therefore, it is important in reducing the clock skew to minimize the delay time in the clock tree portion. Because the relay buffers drive a large number of flip-flops and long wiring lines in the clock tree, a load to be driven is extremely high. Accordingly, to reduce the delay time in the clock tree portion, it is necessary to increase the size of each transistor.
In general, when the size of a transistor is increased, an amount of a current flowing in each of the source and drain thereof increases. As a result, the density of a current in wiring increases so that electromigration causes a problem when the current density exceeds a given threshold. To reduce the current density, it can be considered to increase a power source wiring width and a signal wiring width in accordance with a standard cell which consumes highest power. However, when these wiring widths are increased, a wiring area needed by signal lines increases. This may possibly cause an increase in the area of the semiconductor integrated circuit device and a short circuit in signal wiring due to wiring congestion.
To prevent this, there is proposed a semiconductor integrated circuit device constructed by preparing plural types of standard cells for which power source lines have different widths in accordance with, e.g., the positions at which they are placed (specifically, distances from power source straps) and with the minimum current capacitance of ground wiring and combining these standard cells to prevent an area increase and wiring congestion, while reducing the current density (see, e.g., Japanese Patent Publication No. 2751742).
However, the semiconductor integrated circuit device in which the widths of power source lines are varied depending on the positions at which they are placed does not necessarily lead to effective prevention of electromigration.
For example, there is a case where a standard cell for driving a clock signal is placed at the middle between the power source straps in order to construct a clock tree with equal wiring lengths. In this case, even though the standard cell at the middle portion is composed of large-size transistors, the width of the power source line is smaller at the middle portion between the power source straps so that the current density in the power source line increases undesirably.